1. Field of the Invention
The present invention relates generally to semiconductor circuits and, more particularly, to a method of forming low power programmable elements, and semiconductor devices including low power programmable elements formed by such method.
2. Description of the Related Art
There are a significant number of integrated circuit applications that require some sort of electrically programmable memory for storing information. The information stored varies widely in size ranging from a few bits used to program simple identification data, to several megabits used to program computer operating code. To accommodate the increased demand for electrically programmable memory in modern integrated circuits, a number of well known memory technologies that include, for example, programmable read only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), field programmable gate arrays (FPGAs), and antifuse devices have been readily used. However, fabricating these types of memory devices along with core logic integrated circuitry adds a number of additional processing steps that unfortunately drive up product costs. The additional product costs are often times difficult to justify when only relatively small amounts of electrically programmable elements are needed for a particular integrated circuit application.
To reduce costs, semiconductor designers have been implementing "fuse" structures that are made out of existing doped polysilicon layers that are typically patterned to define transistor gates over a semiconductor structure. Once formed, the fuse structure may be "programmed" by passing a sufficiently high current that melts and vaporizes a portion of the polysilicon fuse. In the programmed state, the fuse structure typically has a resistance that is substantially greater than the non-programmed state, thereby producing an open circuit. This is of course counter to antifuse devices that become short circuits (i.e., substantially decreased resistance) in a programmed state. Although traditional fuse structures work well, they typically consume a large amount of power in programming that may make them unfit for a variety of low power integrated circuit products.
For example, the power dissipated in programming a fuse structure is given by the expression V.sup.2 /R, where V is the voltage applied to the fuse, and R is the resistance. As is well known, the applied voltage must be sufficiently large in order to cause a programming event (e.g., produce an open circuit) in the doped polysilicon fuse structure. Oftentimes, these voltage levels may be larger than the power supplies used by many advanced integrated circuits.
Besides consuming substantial amounts of power to cause the doped polysilicon fuse structure to be programmed, special high voltage transistors are typically designed routed and interconnected over the semiconductor chip itself to direct the increased programming voltages to selected fuses. Consequently, the special high voltage transistors occupy additional chip surface area, thereby causing an increase in chip dimensions, and thereby increasing product costs.
Further, fuse technology has been gaining increased popularity in a variety of consumer electronics, that store confidential information such as pin numbers, bank account numbers, social security numbers and other confidential information directly on a chip. Because this type of information is of such confidential nature, it is critical that such integrated products having fuse programmed data be difficult to reverse engineer. However, a number of fuse structures having distinct advantages are patterned in distinguishing "bow-tie" shapes to facilitate programming in the vicinity of a narrow neck area. For more information on the advantages of bow-tie shaped fuse structures, reference may be made to co-pending U.S. patent application Ser. No. 08/774,036, which is incorporated by reference herein. Although the narrow neck area facilitates programming, it also makes fuse detection rather straight forward for persons attempting to reverse engineer the fuse structures to illegally gain access to confidential information programmed therein.
Accordingly, in view of the foregoing, there is a need for a method of fabricating fuse structures that utilize relatively small amounts of programming power and are difficult to identify during improper reverse engineering attempts.